This invention relates to a power-Up detector for a phase-locked loop (PLL) circuit and more specifically to a PLL circuit for, inter alia, a switching regulator for a cellular telephone.
A PLL circuit is typically employed as a frequency synthesizer, analog modulator or demodulator and can be used in power regulators, communication circuits, clock synthesizers, and frequency synchronization circuits. A basic PLL circuit requires three parts: a phase/frequency detector (PFD), a loop filter, commonly a low-pass filter, and a voltage-control led oscillator (VCO). A conventional configuration is to utilize a charge pump between the output of the PFD and the input to the VCO.
The PFD is responsive to two signals, an input reference signal and the output of the VCO, which is fed back to an input of the PFD. The PFD produces two output signals, UP and DOWN that are used to control the output frequency of the VCO. When the signal fed back to the PFD is substantially the same frequency and phase as the input reference signal, the PLL circuit is said to be phase-locked and the UP and DOWN signal both assume a state which indicates this condition, typically a logic low state. If the input reference signal makes a transition and this transition lags the transition of the VCO output signal going in the same direction, the DOWN signal will pulse high for the duration of the lag time between the signals. If the output signal makes a transition and this transition lags the transition of the input reference signal going in the same direction, the UP signal will pulse high for the duration of the lag time between the signals. The UP and DOWN signals are utilized to control the frequency of the VCO as is well known in the art. Until the reference and the VCO output are near or at equal phase and frequency synchronization, or in a "locked" stated, the PLL will run at some indeterminate frequency and duty cycle. This will create problems for duty cycle sensitive circuits such as switching regulators used in power management integrated circuits.
For example, if at power-up when the PLL circuit has not yet achieved "lock", the PLL circuit outputs a clock signal with a long duty cycle and period causing the switching transistor of a boost mode switching regulator on a power management IC to be ON for an extended period, resulting in the saturation of the inductor core of the switching regulator without supplying current to the load. A voltage-control mode switching regulator would then keep sinking high amount of current through the switching transistor until the PLL output clock signal makes a transition to turn off the switching transistor.
The current will eventually decrease and regulator output stabilize to the target value as the PLL circuit nears lock and the duty cycle and frequency reach a steady state. Thus, to reduce the high current waste in the switching regulator at device startup, the PLL circuit must either quickly power-up at the correct frequency and duty cycle, or the PLL output clock must be masked (not allowing the switching regulator to operate) until such time after power-up that the frequency and duty cycle both stabilize to their steady-state values.
Prior art PLL circuit power-up detectors can be categorized into three groups:
Those circuits that use a binary counter to count the number of reference cycles, enabling the power-up signal after a pre-programmed number of cycles are counted. If RC (low pass) filtered UP/DOWN pulses are detected, the counters are reset to turn off the power-up signal.
Circuits that use a RC circuit that discharges whenever there is a non-zero pulse generated by the RC (low pass) filtered UP/DOWN signals. When the PLL circuit is nearly locked, the RC charging circuit is allowed to charge up to a logic high, activating the power-up signal.
Circuits that use a pulse width filter on the UP/DOWN pulses to control the charging of a switched capacitor. When the pulse width is less than a predetermined threshold the switched capacitor is allowed to charge up. After a certain number of reference clock cycles the capacitor voltage trips a switch to activate the power-up signal. If the UP/DOWN pulse width is longer than the predetermined value, the switched capacitor is discharged and the power-up signal activation signal is delayed. A circuit of this type is shown in the U.S. Pat. No. 5,724,007. Circuits of this type are subject to variations in operation caused by device operating conditions and variations in component values resulting from process variations.